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1454 Commits

Author SHA1 Message Date
CTCaer 0215d16405 Bump hekate to v6.0.4 and Nyx to v1.5.4 2023-06-09 11:08:13 +03:00
CTCaer c0c0e34ef0 nyx: info: update dram info 2023-06-09 11:04:31 +03:00
CTCaer 581ac8ec33 nyx: info: always report errors for eMMC 
Even if init fails.
 2023-06-09 11:04:07 +03:00
CTCaer 26bf148188 nyx: add Lite gamepad calibration data dumping 
Adds calibration data dumping via the Joycon BT pairing dumping function.

Calibration for everything about Sio is dumped. So Sticks and IMU.
 2023-06-09 11:03:29 +03:00
CTCaer dc8f6beb8d nyx: info: make cal0 dumping public 2023-06-09 11:01:08 +03:00
CTCaer 25b181bf36 nyx: add missing newlines 
Change line since the text does not fit like that in these places, effectively breaking text color.
 2023-06-09 10:59:03 +03:00
CTCaer 66e5e128f6 l4t: adjust revision amidst the new changes 
Also add helpful message if files are missing.
 2023-06-09 10:56:39 +03:00
CTCaer 84822726cb l4t: add fine tuned voltage support for DRAM 
1000-1175mV for T210 VDDIO/Q via `ram_oc_vdd2`
1000-1175mV for T210B01 VDDIO and 600-650mV for VDDQ via `ram_oc_vdd2` and `ram_oc_vddq`.
 2023-06-09 10:55:32 +03:00
CTCaer b6e1e0d412 l4t: add bpmp-fw support for T210 2023-06-09 10:53:03 +03:00
CTCaer 496737248c l4t: there was never a need to normalize dram freq 2023-06-09 10:51:31 +03:00
CTCaer 4f52e1f24a l4t: refactor bpmp-fw defines for T210B01 2023-06-09 10:50:29 +03:00
CTCaer 3f9c7a7da6 hos: prep boot freq in minerva for cfw also 2023-06-09 10:41:53 +03:00
CTCaer 93ed4d0899 bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
CTCaer 01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer 191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer 8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer 18f3a1b70c bdk: max77620: reduce max DRAM VDDIO/Q 
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
 2023-06-09 10:24:55 +03:00
CTCaer 418f029d11 lib: minerva: add 1966 and 2033 MHz in div table 2023-06-08 05:31:15 +03:00
CTCaer 066efda4cd lib: minerva: normalize output frequency 
Allow frequencies that are not exact to receive proper dividers from the supported ones from table.
 2023-06-08 04:56:14 +03:00
CTCaer d8d15bde44 lib: minerva: add Samsung 8GB support 
And remove frequencies smaller than deep sleep frequency from the tables.
 2023-06-08 04:50:59 +03:00
CTCaer 9d8ebc7e38 lib: minerva: refactor table 
Remove _idx used initially for RE at last.
 2023-06-08 04:49:16 +03:00
CTCaer c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210 
And remove Copper support completely.
 2023-06-08 04:16:51 +03:00
CTCaer 73a133556d bdk: sdram: correct sku related info 
Validated so rename accordingly.
 2023-06-08 02:57:30 +03:00
CTCaer 7d3663616e bdk: sdram: name 2 of the new ram chips 
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
 2023-06-08 02:52:03 +03:00
CTCaer e76aebabba bdk: mem: minerva: check table size in clock check 
Don't hardcode table size to 10.
 2023-06-08 02:45:34 +03:00
CTCaer bc0eea11f3 bdk: joycon: add calibration struct 2023-06-08 02:44:35 +03:00
CTCaer 937ab52d14 Bump hekate to v6.0.4 2023-05-09 11:15:34 +03:00
CTCaer e896d388ab hos: 16.0.3 support 2023-05-09 11:15:11 +03:00
CTCaer ded959c449 Bump hekate to v6.0.3 and Nyx to v1.5.3 2023-04-06 17:38:36 +03:00
CTCaer a7fd83c793 nyx: correct build flag 2023-04-06 17:36:22 +03:00
CTCaer dd380d4d47 l4t: increase bw priority to SDMMC1 for L4T 2023-04-06 17:34:26 +03:00
CTCaer 795b4ad26e bdk: sdmmc: increase bw priority to SDMMC1 for L4T 2023-04-06 17:30:01 +03:00
CTCaer bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00
CTCaer 811fa4c88b bdk: sdmmc: add SD registers debug printing 
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
 2023-04-06 10:13:35 +03:00
CTCaer 22462e4bf3 nyx: info: optimize random benchmarking 
Do not allow SD/eMMC to breath during random reads benchmarking. So only render progress at 15fps.
 2023-03-31 09:24:55 +03:00
CTCaer ca0263fa8c hekate: info: fully deinit/unmount sd card 2023-03-31 09:17:51 +03:00
CTCaer b1112e0949 hos: set proper exo hos version for 12.1.0 
Even if 12.0.0 one is api compatible, there was a master key change on 12.1.0.
 2023-03-31 09:17:13 +03:00
CTCaer 3c3fcb29f9 hekate: clear rtc interrupt and stop alarm 
Stopping rtc alarm is now done in the function that actually checks it, in order to avoid power offs from HOS if it's fired and user wants to continue booting.

Additionally, clear the interrupt which is the actual thing that is checked by HOS.
 2023-03-31 09:15:56 +03:00
CTCaer 8528e6a08a bdk: util: do not edit rtc alarm in power function 2023-03-31 09:12:58 +03:00
CTCaer 27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer 50811aacfa bdk: touch: reorder power on 
So touch IC reset can be properly done on a fast power cycle.
 2023-03-31 09:08:20 +03:00
CTCaer f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer d258c82d52 bdk: sdmmc: add UHS DDR200 support 
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
 2023-03-31 08:54:13 +03:00
CTCaer 7f32c6d211 bdk: sd: better removal detection handling 2023-03-31 08:31:20 +03:00
CTCaer 2f7e841b50 bdk: sdmmc: move sdr12 setup for better readability 2023-03-31 08:29:20 +03:00
CTCaer 29e32f09fb bdk: sdmmc: properly identify sdmmc1 clk config 
Remove schmitt trigger config from clock pin on sdmmc1 for identifying previous pinmuxing state.
 2023-03-31 08:27:48 +03:00
CTCaer b123571c56 bdk: sdmmc: only allow power raise if SDR50 and up 
As per spec.
 2023-03-31 08:26:19 +03:00
CTCaer b7164a629f bdk: sdmmc: allow max power limit to be set 
Even if it defaults to 1.44W.
Some cards' firmware maybe be bugged.

The 3.3V regulator on all SKUs allow more than 800mA current anyway.
 2023-03-31 08:24:52 +03:00