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40 Commits

Author SHA1 Message Date
CTCaer feb5b11f66 minerva: do not reread mrr for channel b 
Just in case the mrr fifo is not empty.
 2024-02-16 16:34:30 +02:00
CTCaer bd1733c4fa minerva: use min 2 divm 
Adhere to software based imposed limits for T210.
 2023-12-25 04:11:55 +02:00
CTCaer bb0a1fd0a2 minerva: add freqs up to 2366 MHz 2023-07-31 17:05:09 +03:00
CTCaer 418f029d11 lib: minerva: add 1966 and 2033 MHz in div table 2023-06-08 05:31:15 +03:00
CTCaer 066efda4cd lib: minerva: normalize output frequency 
Allow frequencies that are not exact to receive proper dividers from the supported ones from table.
 2023-06-08 04:56:14 +03:00
CTCaer d8d15bde44 lib: minerva: add Samsung 8GB support 
And remove frequencies smaller than deep sleep frequency from the tables.
 2023-06-08 04:50:59 +03:00
CTCaer 9d8ebc7e38 lib: minerva: refactor table 
Remove _idx used initially for RE at last.
 2023-06-08 04:49:16 +03:00
CTCaer 5193416658 hekate/nyx: stylistic corrections 2023-02-11 23:51:43 +02:00
CTCaer 9c1238f99d Update Warnings flags in makefiles 2022-10-11 07:25:21 +03:00
CTCaer 20c4d6dba6 minerva: update copyright years 2022-01-20 13:22:39 +02:00
CTCaer 6a74f6ed04 minerva: make is_pllmb and fsp automatic 
No need to keep these values around.
Software will automatically check the proper registers to get status.
 2022-01-16 01:43:16 +02:00
CTCaer d1c0d464dc minerva: name needs_training flags 2022-01-16 01:41:24 +02:00
CTCaer 339ce2d861 minerva: change some types and fix temp check 
Temperature error check for over temp compensation was wrong.

It's still unused though, so it didn't matter.
 2021-10-15 16:48:51 +03:00
CTCaer d61be73bca nyx: add reminder that reload also checks for update.bin 2021-09-17 23:34:16 +03:00
CTCaer d575586d77 minerva: add non standard frequencies selection 2021-08-28 18:11:29 +03:00
CTCaer 05833bb38c minerva: update to v1.4 
- Correct Zqlatch period checks
- Update periodic training
- Simplify some logic
- Fix some mr13 values
- Separate EMC channel enums from macros
- Add extra reg flushes
- Fix tree margin comparison signedness
 By using incorrect signedness on tree margins the delta taps would always apply.
 By casting margins to integer it now properly checks if it should apply delta taps on the new trimmers.
 This fixes a bug that exists in every Nvidia emc dvfs code.
 2021-05-11 10:23:08 +03:00
CTCaer 07d1982abf minerva: add compile time sdram voltage change 2021-04-11 10:31:57 +03:00
CTCaer faf5651607 minerva: more accurate clock tree delays 
Additionally, do not restore source DPD ctrl when switching frequencies or training is not needed.
 2021-04-11 09:50:06 +03:00
CTCaer 8ce5d55eb8 mtc: Confine RAM OC completely inside minerva 
Enabling OVERCLOCK_FREQ takes care of everything without the need of changing minerva caller.
 2021-01-03 14:37:39 +02:00
CTCaer afb749560a mtc: Fix temperature deltas for clk tree delays when negative 2021-01-03 14:35:21 +02:00
CTCaer 7a66e0298a mtc: Refactor various types 2021-01-03 14:33:56 +02:00
CTCaer dfcdb2e1e6 mtc: Update minerva to simplify some logic 2020-12-26 17:28:49 +02:00
CTCaer d0a73bdc72 sc7: Add T210B01 SC7/LP0 (deep sleep) support 
Note to future self: Almost a month passed and nothing changed, have fun cleaning that in the end...
 2020-06-26 19:00:30 +03:00
CTCaer 46fa330bdd Add proper make prints for modules 2020-07-18 01:36:16 +03:00
CTCaer d37fe213d7 mtc: Name sdram ids 2020-06-14 17:39:39 +03:00
CTCaer 6e256d29c7 Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
CTCaer 27926b0d55 Allow automatic inlining for modules 2020-06-13 18:40:09 +03:00
CTCaer 8ce6bf82a9 Minimize make info noise during building 2020-06-13 18:39:17 +03:00
CTCaer a52af1bf41 Fix building on make 4.3 2020-03-04 01:34:35 +02:00
CTCaer 84328aa676 minerva: Make use of new minerva 
- Training and switch is now faster
- Compatibility checks: New Minerva does not allow old binaries. New binaries do not allow old Minerva
- MTC table is now in a safe region
- Periodic training period increased to every 250ms
 2019-12-04 21:56:45 +02:00
CTCaer 66c4f30bdf minerva: Update to v1.2 and use only integers 
Additionally remove support for DRAM types that Switch platform does not have.

This will reduce periodic training cost to 30us from 6ms.
 2019-12-04 21:46:33 +02:00
Kostas Missos 7c42f72b8a refactor: Remove all unwanted whitespace 2019-10-18 18:02:06 +03:00
ctcaer@gmail.com 52478833de [MTC] Utilize Minerva Training Cell 2019-06-30 03:49:33 +03:00
Kostas Missos cfef8b4f72 Update libminerva to v1.1 2018-11-10 13:30:17 +02:00
Kostas Missos ec1bb508b3 Fix minerva build 
This is still for testing it out.
The real usage will come later.
 2018-11-05 10:54:31 +02:00
Kostas Missos cae9044c17 Minerva our DRAM trainer 
Supports up to 1600MHz and periodic training.

For more check here: https://github.com/CTCaer/minerva_tc
 2018-11-04 03:15:32 +02:00
Kostas Missos 58b289bee2 Fix build pf sample module by adding missing files 2018-08-25 22:59:54 +03:00
Kostas Missos 1d623eacf9 Our 1st module. LP0 configuration. 2018-08-21 04:14:31 +03:00
Kostas Missos e5abdd938e Refactor ALL the things + enable LTO 2018-08-13 11:58:24 +03:00
M4xw 8b0915cb01 Implement elfloader/module support 2018-08-07 22:41:05 +02:00