529 lines
12 KiB
C
529 lines
12 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "../soc/clock.h"
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#include "../soc/t210.h"
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#include "../utils/util.h"
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#include "../storage/sdmmc.h"
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/* clock_t: reset, enable, source, index, clk_src, clk_div */
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static const clock_t _clock_uart[] = {
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/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 },
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/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 },
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/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 0x17, 0, 0 },
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/* UART D */ { 0 },
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/* UART E */ { 0 }
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};
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static const clock_t _clock_i2c[] = {
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/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 },
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/* I2C2 */ { 0 },
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/* I2C3 */ { 0 },
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/* I2C4 */ { 0 },
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/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 },
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/* I2C6 */ { 0 }
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};
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static clock_t _clock_se = {
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CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0
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};
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static clock_t _clock_unk2 = {
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CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 0x1E, 0, 0
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};
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static clock_t _clock_host1x = {
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CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3
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};
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static clock_t _clock_tsec = {
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CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2
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};
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static clock_t _clock_sor_safe = {
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CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 0x1E, 0, 0
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};
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static clock_t _clock_sor0 = {
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CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 0x16, 0, 0
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};
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static clock_t _clock_sor1 = {
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CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2
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};
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static clock_t _clock_kfuse = {
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CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0
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};
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static clock_t _clock_cl_dvfs = {
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CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 0x1B, 0, 0
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};
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static clock_t _clock_coresight = {
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CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4
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};
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static clock_t _clock_pwm = {
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CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4
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};
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void clock_enable(const clock_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~(1 << clk->index);
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// Configure clock source if required.
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if (clk->source)
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CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
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// Enable.
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CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
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// Take clock off reset.
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CLOCK(clk->reset) &= ~(1 << clk->index);
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}
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void clock_disable(const clock_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~(1 << clk->index);
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}
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void clock_enable_fuse(bool enable)
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{
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CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28);
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}
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void clock_enable_uart(u32 idx)
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{
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clock_enable(&_clock_uart[idx]);
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}
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void clock_enable_i2c(u32 idx)
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{
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clock_enable(&_clock_i2c[idx]);
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}
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void clock_disable_i2c(u32 idx)
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{
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clock_disable(&_clock_i2c[idx]);
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}
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void clock_enable_se()
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{
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clock_enable(&_clock_se);
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}
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void clock_enable_unk2()
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{
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clock_enable(&_clock_unk2);
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}
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void clock_enable_host1x()
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{
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clock_enable(&_clock_host1x);
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}
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void clock_disable_host1x()
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{
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clock_disable(&_clock_host1x);
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}
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void clock_enable_tsec()
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{
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clock_enable(&_clock_tsec);
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}
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void clock_disable_tsec()
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{
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clock_disable(&_clock_tsec);
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}
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void clock_enable_sor_safe()
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{
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clock_enable(&_clock_sor_safe);
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}
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void clock_disable_sor_safe()
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{
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clock_disable(&_clock_sor_safe);
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}
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void clock_enable_sor0()
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{
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clock_enable(&_clock_sor0);
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}
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void clock_disable_sor0()
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{
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clock_disable(&_clock_sor0);
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}
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void clock_enable_sor1()
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{
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clock_enable(&_clock_sor1);
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}
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void clock_disable_sor1()
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{
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clock_disable(&_clock_sor1);
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}
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void clock_enable_kfuse()
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{
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//clock_enable(&_clock_kfuse);
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100;
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usleep(10);
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF;
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usleep(20);
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}
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void clock_disable_kfuse()
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{
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clock_disable(&_clock_kfuse);
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}
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void clock_enable_cl_dvfs()
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{
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clock_enable(&_clock_cl_dvfs);
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}
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void clock_disable_cl_dvfs()
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{
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clock_disable(&_clock_cl_dvfs);
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}
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void clock_enable_coresight()
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{
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clock_enable(&_clock_coresight);
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}
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void clock_disable_coresight()
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{
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clock_disable(&_clock_coresight);
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}
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void clock_enable_pwm()
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{
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clock_enable(&_clock_pwm);
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}
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void clock_disable_pwm()
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{
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clock_disable(&_clock_pwm);
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}
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC4_RST (1 << 15)
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#define U_SWR_SDMMC3_RST (1 << 5)
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#define L_CLK_ENB_SDMMC1 (1 << 14)
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#define L_CLK_ENB_SDMMC2 (1 << 9)
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#define L_CLK_ENB_SDMMC4 (1 << 15)
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#define U_CLK_ENB_SDMMC3 (1 << 5)
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#define L_SET_SDMMC1_RST (1 << 14)
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#define L_SET_SDMMC2_RST (1 << 9)
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#define L_SET_SDMMC4_RST (1 << 15)
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#define U_SET_SDMMC3_RST (1 << 5)
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#define L_CLR_SDMMC1_RST (1 << 14)
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#define L_CLR_SDMMC2_RST (1 << 9)
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#define L_CLR_SDMMC4_RST (1 << 15)
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#define U_CLR_SDMMC3_RST (1 << 5)
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#define L_SET_CLK_ENB_SDMMC1 (1 << 14)
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#define L_SET_CLK_ENB_SDMMC2 (1 << 9)
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#define L_SET_CLK_ENB_SDMMC4 (1 << 15)
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#define U_SET_CLK_ENB_SDMMC3 (1 << 5)
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#define L_CLR_CLK_ENB_SDMMC1 (1 << 14)
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#define L_CLR_CLK_ENB_SDMMC2 (1 << 9)
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#define L_CLR_CLK_ENB_SDMMC4 (1 << 15)
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#define U_CLR_CLK_ENB_SDMMC3 (1 << 5)
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static int _clock_sdmmc_is_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC1_RST;
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case SDMMC_2:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC2_RST;
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case SDMMC_3:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & U_SWR_SDMMC3_RST;
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case SDMMC_4:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC4_RST;
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}
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return 0;
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}
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static void _clock_sdmmc_set_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC1_RST;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC2_RST;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = U_SET_SDMMC3_RST;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC4_RST;
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break;
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}
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}
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static void _clock_sdmmc_clear_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC1_RST;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC2_RST;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = U_CLR_SDMMC3_RST;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC4_RST;
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break;
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}
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}
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static int _clock_sdmmc_is_enabled(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC1;
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case SDMMC_2:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC2;
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case SDMMC_3:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & U_CLK_ENB_SDMMC3;
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case SDMMC_4:
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return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC4;
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}
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return 0;
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}
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static void _clock_sdmmc_set_enable(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC1;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC2;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = U_SET_CLK_ENB_SDMMC3;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC4;
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break;
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}
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}
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static void _clock_sdmmc_clear_enable(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC1;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC2;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = U_CLR_CLK_ENB_SDMMC3;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC4;
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break;
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}
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}
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static u32 _clock_sdmmc_table[8] = { 0 };
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#define PLLP_OUT0 0x0
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static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
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{
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u32 divisor = 0;
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u32 source = PLLP_OUT0;
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switch (val)
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{
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case 25000:
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*pout = 24728;
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divisor = 31;
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break;
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case 26000:
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*pout = 25500;
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divisor = 30;
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break;
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case 40800:
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*pout = 40800;
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divisor = 18;
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break;
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case 50000:
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*pout = 48000;
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divisor = 15;
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break;
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case 52000:
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*pout = 51000;
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divisor = 14;
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break;
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case 100000:
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*pout = 90667;
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divisor = 7;
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break;
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case 200000:
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*pout = 163200;
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divisor = 3;
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break;
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case 208000:
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*pout = 204000;
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divisor = 2;
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break;
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default:
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*pout = 24728;
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divisor = 31;
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}
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_clock_sdmmc_table[2 * id] = val;
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_clock_sdmmc_table[2 * id + 1] = *pout;
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switch (id)
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{
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case SDMMC_1:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = (source << 29) | divisor;
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break;
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case SDMMC_2:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = (source << 29) | divisor;
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break;
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case SDMMC_3:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = (source << 29) | divisor;
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break;
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case SDMMC_4:
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = (source << 29) | divisor;
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break;
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}
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return 1;
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}
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
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{
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if (_clock_sdmmc_table[2 * id] == val)
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{
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*pout = _clock_sdmmc_table[2 * id + 1];
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}
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else
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{
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int is_enabled = _clock_sdmmc_is_enabled(id);
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if (is_enabled)
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_config_clock_source_inner(pout, id, val);
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if (is_enabled)
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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}
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}
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void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type)
|
|
{
|
|
switch (type)
|
|
{
|
|
case 0:
|
|
*pout = 26000;
|
|
*pdivisor = 66;
|
|
break;
|
|
case 1:
|
|
*pout = 26000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case 2:
|
|
*pout = 52000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
case 11:
|
|
*pout = 200000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case 5:
|
|
*pout = 25000;
|
|
*pdivisor = 64;
|
|
break;
|
|
case 6:
|
|
case 8:
|
|
*pout = 25000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case 7:
|
|
*pout = 50000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case 10:
|
|
*pout = 100000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case 13:
|
|
*pout = 40800;
|
|
*pdivisor = 1;
|
|
break;
|
|
case 14:
|
|
*pout = 200000;
|
|
*pdivisor = 2;
|
|
break;
|
|
}
|
|
}
|
|
|
|
int clock_sdmmc_is_not_reset_and_enabled(u32 id)
|
|
{
|
|
return !_clock_sdmmc_is_reset(id) && _clock_sdmmc_is_enabled(id);
|
|
}
|
|
|
|
void clock_sdmmc_enable(u32 id, u32 val)
|
|
{
|
|
u32 div = 0;
|
|
|
|
if (_clock_sdmmc_is_enabled(id))
|
|
_clock_sdmmc_clear_enable(id);
|
|
_clock_sdmmc_set_reset(id);
|
|
_clock_sdmmc_config_clock_source_inner(&div, id, val);
|
|
_clock_sdmmc_set_enable(id);
|
|
_clock_sdmmc_is_reset(id);
|
|
usleep((100000 + div - 1) / div);
|
|
_clock_sdmmc_clear_reset(id);
|
|
_clock_sdmmc_is_reset(id);
|
|
}
|
|
|
|
void clock_sdmmc_disable(u32 id)
|
|
{
|
|
_clock_sdmmc_set_reset(id);
|
|
_clock_sdmmc_clear_enable(id);
|
|
_clock_sdmmc_is_reset(id);
|
|
}
|